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EE 272: Design Projects in VLSI Systems

An introduction to mixed signal design. Working in teams you will create a small mixed-signal VLSI design using a modern design flow and CAD tools. The project involves writing a Verilog model of the chip, creating a testing/debug strategy for your chip, wrapping custom layout to fit into a std cell system, using synthesis and place and route tools to create the layout of your chip, and understanding all the weird stuff you need to do to tape-out a chip. Useful for anyone who will build a chip in their Ph.D. Pre-requsiites: EE271 and experience in digital/analog circuit design.
Terms: Win | Units: 3-4 | Grading: Letter or Credit/No Credit
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